Presents a CPU Design for LC-3 instruction set, that we later implement using Verilog HDL. The illustrations help visualize the design. The instruction set is based on the book Introduction to Computer Systems by Patt and Partel. For this text we push the simplicity of this little microprocessor (LC-3) even further as described in Instruction Set.
Design
The microprocessor consists of a Data Path and a Control Unit. Together they implement the various instruction phases.
This section describes an architecture for the LC-3. It aims at staying true to the von Neumann architecture and instruction cycle names. However, here we assume the program counter and instruction register are in the data path.
Data Path
The schematic below shows the Data Path.
We use the following conventions
- The shaded blocks are modules that implement various functionality. The module names have been chosen to reflect the instruction phases.
- Signals connect the blocks. A signal can be a single wire, or a collection of wires such as the 16 bits that represent the value of the program counter. Signal names are chosen to overlap with operand names where possible.
- The microprocessor connects to an external memory through the external interface.
Modules
Module | Description |
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Maintains the program counter, |
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Initiates the bus cycle, to read the instruction pointed to by |
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Reads the instruction from the memory bus and extracts its operands. |
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Maintains the register values and processor status register. |
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Performs arithmetic and logical operations. |
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Calculates memory address for memory or control instructions. |
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Initiates the external memory bus cycle to read or write data. |
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Destination register multiplexor, selects the value that will be written to the destination register. |
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Simple arbiter for memory read requests from |
Signals
Group | Signal | Description |
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Program counters | Program Counter | |
Next program counter (always has the value +1 ) |
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Target program counter, for |
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Operands | Source register 1 identifier. Also used as baseRID for |
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Source register 2 identifier. Also used as srID for |
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Immediate value | ||
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Memory address offset | |
Register values | Value of the register identified by signal |
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Value of the register identified by
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Value written to the register identified by |
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Value of the processor status register | ||
Intermediate values | Result of the ALU operation | |
Result of the address calculation | ||
External bus | Memory address | |
Instruction/data being read from memory | ||
Data being written from memory | ||
Write enable signal going to memory. Value 0 for read, 1 for write. |
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Internal bus | Internal bus request signals | |
Internal memory addresses | ||
Internal write enable signals |
Examples
Read memory
Assume: the instruction at address 3000
is 201F
.
Assigning the label LDv
to memory location 3020
, this instruction decodes to
Address | Value | Label | Mnemonic |
---|---|---|---|
x3000 | x201F | LD r0, LDv | |
x3020 | x1234 | LDv |
Issuing a reset, triggers the following sequence of events:
# | Module | Action | Signals |
---|---|---|---|
1. |
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Resets the program counter to its initial value |
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2. |
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Starts a read cycle for the instruction |
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3. |
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Forwards the read cycle to the external memory bus |
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4. |
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Responds with the instruction |
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5. |
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Extracts the operands |
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6. |
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Adds the |
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7. |
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Starts a read cycle for the data |
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8. |
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Forwards the read cycle to the external memory bus |
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9. |
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Responds with the data |
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10. |
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Selects the |
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11. | Writes the value |
ALU operation
Assume: R0=1234
and R1=4321
. The instruction at the next address 3004
is 1801
.
This instruction decodes to
Address | Value | Label | Mnemonic |
---|---|---|---|
x3004 | x1801 | ADD R4, R0, R1 |
The following sequence of events will happen:
# | Module | Action | Signals |
---|---|---|---|
1. |
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Increments the program counter |
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2. |
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Starts a read cycle for the instruction |
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3. |
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Forwards the read cycle to the external memory bus |
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4. |
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Responds with the instruction |
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5. |
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Extracts the operands |
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6. |
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Supplies the values for the registers identified by |
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7. |
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Calculates the sum of | .
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8. |
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Selects the |
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9. |
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Writes the value |
Write memory
Assume: R4=AAAA
and the label STIa
refers to data address 3024
containing the value 3028
. The instruction at the next address 3008
is B81D
.
This instruction decodes to
Address | Value | Label | Mnemonic |
---|---|---|---|
x3008 | xB81D | STI R4, STIa | |
x3024 | x3028 | STIa | |
x3028 | xBAD0 |
The following sequence of events will happen:
# | Module | Action | Signals |
---|---|---|---|
1. |
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Increments the program counter |
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2. |
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Starts a read cycle for the instruction. |
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3. |
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Forwards the read cycle to the external memory bus. |
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4. |
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Responds with the instruction. |
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5. |
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Extracts the operands (sr2ID represents the SR operand)
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6. |
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Supplies the value for the register identified by |
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7. |
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Adds the | .
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8. |
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Starts a read cycle to retrieve the address where to store the value. |
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9. |
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Forwards the read cycle to the external memory bus. |
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10. |
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Responds with the value |
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11. |
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Starts a write cycle to write the value of register R4 to address 3028 |
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12. |
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Forwards the write cycle to the external memory bus. |
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Control unit
Instructions can be broken up into micro instructions. These can be implemented using a finite state machine (FSM), where each state corresponds to one micro instruction.
The finite state machine can be visualized as shown in the figure below.
- circles, represent the states identified by a unique number and name.
- double circle, represents the initial state.
- arrows, represent state transitions. Labels represent the condition that must be met for the transition to occur.
- shading, is used to identify the implementation modules.
-
eREADY , indicates that the external memory finished a read or write operation. -
iType ,maType ,indType refer to the generalized instruction types generated by Decoder.
State diagram
Details
- Policies:
- State transitions, are only possible during the falling edge of the clock signal (from 1 to 0);
- Outputs, to the external memory interface, are driven in response to state transitions;
- Inputs, from the external memory interface, are sampled on the rising edge of the clock signal (from 0 to 1);
- Control signals, change only during the falling edge of the clock signal to minimize glitches.
- Each state:
- depends on both input signals and the previous state’
- generates control signals control signals for the data path (with the help of the Decode module).
- The control unit consists of two modules:
- State, implements the state machine, and generates state specific control signals.
- Decode, generalizes the instruction for the state machine, and generates state independent control signals.
Schematic for the control unit
The next section describes the signals for the control unit in the CPU Design for LC-3 instruction set.
Signals for the control unit
Group | Signal | Description |
---|---|---|
External interface |
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Indicates that the external memory finished a read or write operation. |
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External supplied clock | |
Internal to the State module |
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Current state |
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Next state as determined by the combinational logic | |
Generalized instruction types (bundled into |
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Instruction type |
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Memory access type | |
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Indirect memory access type | |
Data path control |
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Signals |
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Enables |
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Enable |
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Enables |
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Enables |
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Chooses the operation and inputs of the |
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Chooses the operation and inputs of the |
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Chooses the memory operation to be performed by |
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Selects the destination register source input on |
The next section gives a detailed description of the modules for the CPU Design for LC-3 instruction set.
Modules (detailed description)
Module | Description |
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Generates the state specific control signals for each micro instruction being executed. Refer to the signals described above for details. |
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Updates the program counter,
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*) DrMux is an abbreviation for Destination Register Multiplexor.