This article describes the physics of Metal Oxide Silicon Field-effect Transistors (MOSFET). It uses these MSOFETs to build logic gates. This is part in a quest to answer the question “How do computers do math?”.\(\)
At first glance, the construction of the MOSFET might appear similar to the JET. However, there are some important differences: (1) a thin layer of silicon dioxide (SiO2) isolates the gate, and (2) they have no obvious conductive channel.
The illustration below shows symbols for, and examples of, MOSFETs.
Semiconductor physics
In the n-channel MOSFET, a p-type substrate connects to the source and drain pins via more heavily doped n+ type regions, as shown below. A very thin layer of silicon dioxide insulates the metal gate terminal from the substrate. A bias over the drain-source terminals causes the depletion layer around the drain to widen. The depletion areas prevent a drain current.
Applying a gate potential \(U_{gs}\) makes the gate positive with respect to the source and substrate, as shown below. The positive charge on the gate repels holes from the p-layer underneath, forming a depletion area. This charge also attracts free electrons from the n+ source and drain that form a thin layer under the gate terminal bridging the source and drain areas. This layer is called an inversion channel because it behaves like a n-type material. The inversion channel is of the same type as the source and drain, and thus it provides a channel through which current can pass.
Any further increase of the gate voltage attracts more electrons into the inversion channel, reducing its resistance and increaing the current between the source and drain. Removing the gate source voltage stops the current leading and the area beneath the gate to revert to p-type. This method of operation is called enhanced mode, because the gate potential “enhances” the conducting channel. There are also devices where a gate potential “depletes” the conducting channel.
Due to the physics of MOSFET, these transistors draw very little power because the gate current is extremely low; they’re as small as 7 nanometers, the width of 10 silicon atoms; and can switch on/off in the order of GHz. This makes them an ideal building block modern day computers that use integrated circuits with trillions of MOSFETs on one piece of silicon.
MOSFET based logic
A voltage input to the gate controls the flow of current from source to drain. Being voltage-controlled rather than current-controlled, it allows for resistor-less circuits. CMOS draws no current other than leakage when in a steady 1 or 0 state. When the gate switches states, it draws current to charge the capacitance at the gate.
To implement logic functions, a complementary pair of MOSFETs can connect an output to either Vcc or ground. The name Complementary Metal Oxide Semiconductor (CMOS) refers to the use of complementary pairs of p-type and n-type MOSFETs. Note that the CMOS voltage levels are 0 volt and 3.3 volts.
NOT gate in CMOS
The circuit shown below gives the most basic implementation of a CMOS gate, where the FETs are used invert a logical input signal.
When a 3.3 volts signal (logic 1) is applied at input \(A\), the n-channel MOSFET is conducting, and the p-channel MOSFET is not, and the output \(X\) is a logic 0. On the other hand, if the input is grounded (logic 0) the situation is reversed, and the output \(X\) is a logic 1. A simulation confirms that the output values stay well within the CMOS range.
| \(U_A\) | \(U_X\) |
|---|---|
| 0.00 V | 3.30 V |
| 3.30 V | 0.00 V |
By extending this NOT gate, we can build NOR and NAND gates.
NOR gate in CMOS
Putting two n-channel MOSFETs in parallel and two p-channel MOSFETs in series, we can create a two-input NOR gate as shown in the circuit below. A simulation confirms that these output values stay perfectly within CMOS range.
| \(U_A\) | \(U_B\) | \(U_X\) |
|---|---|---|
| 0.00 V | 0.00 V | 3.30 V |
| 0.00 V | 3.30 V | 0.00 V |
| 3.30 V | 0.00 V | 0.00 V |
| 3.30 V | 3.30 V | 0.00 V |
NAND gate in CMOS
By putting two n-channel MOSFETs in series and two p-channel MOSFETs in parallel, we can build a two-input NAND gate as shown in the circuit below. Once more, simulation confirms that the output values are at CMOS values.
| \(U_A\) | \(U_B\) | \(U_X\) |
|---|---|---|
| 0.00 V | 0.00 V | 3.30 V |
| 0.00 V | 3.30 V | 3.30 V |
| 3.30 V | 0.00 V | 3.30 V |
| 3.30 V | 3.30 V | 0.00 V |