Field effect transistor

This post describes the semiconductor physics of the Field Effect Transistors (FET). It uses the FET to build logic gates. This is part of a quest to answer the question “How do computers do math?”. Here we introduce an improved transistor type. \(\)

The Field Effect Transistor (FET) can be used as a voltage-controlled resistor.

Lilienfeld and Heil discovered the principle of field-effect as early as 1926-1927 [patent], but it took until well after the invention of the bipolar junction transistor before it became practical to make them (Atalla, 1960). Even though FETs are conceptually simple, they are difficult to manufacture because they require an extremely clean manufacturing environment.

The illustration below shows the symbols for the JFETs.

N-FET Symbol
P-FET Symbol
FET packages

Semiconductor physics

In the n-channel device, the channel is in between two connected p-type regions, as shown in the illustration below. More heavily doped n+ type regions connect the source and drain pins to the n-type channel. This n+ type silicon prevents an unwanted pn-junction between the regular n-type silicon with its four valence electrons and the e.g. aluminum terminal with its three valence electrons.

When we place a modest voltage \(U_{ds}\) over the drain and source, the ions at the depletion layers give the channel a positive charge compared to the gate. The depletion layer is thicker towards the drain end of the channel, as the voltage on the drain is more positive than that on the source due to voltage gradient that exists along the channel. The current flows and the silicon channel acts similarty to a conductor.

(c) 2016 Copyright Coert Vonk
N-channel JFET with Ugs=0

To use this JFET as a switch, we can increase the thickness of the depletion zone by applying a reverse bias on the gate, as shown below. This pushes the holes from the p-type region and the electrons in the n-type region away from the junction, increasing the width of the depletion zone. Eventually, once enough potential is applied, the transistor will pinch off the channel current (\(I_d\)). This pinch off voltage is typically a negative few volts.

To use this JFET as an amplifier, we can increase \(U_{ds}\) while \(U_{gs}=0\). At first, the drain current \(I_d\) will increase, but meanwhile the depletion layer is also growing and narrowing the n-channel. At the so called “pinch-off” value \(U_{p}\), the conducting channel is so narrow that it cancels out the effect of the higher \(U_{ds}\). The \(I_d\) doesn’t increase much further, and the JFET is said to be in saturation mode. At this point, a small \(U_{gs}\) can be used to control the current through the source−drain channel from its maximum value to zero. [learn-electronics]

(c) 2016 Copyright Coert Vonk
N-channel JFET with Ugs

JFET based logic

JFETs have very nice properties, but when used in circuits they still require bulky resistors. As we see in the next section, MOSFETs do not require such resistors.

Enough about FET semiconductor physics and building logic gates. The next chapter introduces an improvement on this Field Effect Transistor.

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