Starting with Xilinx

This describes how to install the development environment for the Avnet’s Xilinx Spartan-6 FPGA LX9 MicroBoard under Windows 10 x64. For Altera boards, refer to Getting started with FPGA design using Altera Quartus Prime. Another interesting Xilinx based board is the XuLA (XC3S200A).

Note 1: you need to be logged into to access the links. This might be the only occasion where I had to use the Edge browser to access the Support & Download area.

Note 2: I can’t describe the install for the ChipScope Pro, because my license expired.

Install the Xilinx ISE Design Suite

  1. ISE Design Suite
    • download version 14.7 from
    • extract the tar file, and run xsetup.exe
    • select ISE WebPACK
    • have some patience.
  2. Xlinx License Manager
    • will start automatically
    • get Free Vivado/ISE WebPack License » next
    • sign in (if needed create an account first)
    • generate a node locked license for ISE WebPACK
    • the Xilinx.lic will arrive as an email attachment
    • click Load License button, and install the license from the email
  3. Running on Windows 10
    • ISE is in maintenance mode, and doesn’t support Windows 10 (or 8.x)
    • According eevblog, crashes with file dialogs in ISE and iMPACT can be prevented by turning off Smart Heap. To do so:
      • rename libPortability.dll to libPortability.dll.orig
      • copy libPortabilityNOSH.dll to libPortability.dll in
    • in
      • C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64
      • C:\Xilinx\14.7\ISE_DS\common\lib\nt64 (copy dll from first location)
  4. See if it starts
    • Double-click the ISE Design Suite icon on your desktop

Install Avnet Board Support

  1. Install the board description (XDB)
    • Install the Spartan-6 FPGA LX9 MicroBoard XDB file from
    • unzip, then again
    • unzip file to the \board folder.
  2. Install USB-to-UART driver
    • Download the CP210x virtual com port driver from
    • Extract, and install by running CP210xVCPInstaller_x64.exe
    • Verify that Serial Port “Silicon Lapbs CP2010x USB to UART Bridge (COMx)” appears in Device Manager when the micro-USB cable is plugged in. For details see the CP210x_setup_guide.
    • Walk through the examples in the board’s Getting Started Guide. Note that instead of HyperTerm, you can use PuTTY.
  3. Install USB-to-JTAG driver
    • Download the Digilent Adept 2.16.1 System.
    • Run the executable to install
    • Verify that the “Digilent USB Controller” appears in Device Manager when the USB Type A plug is plugged in.
  4. Install JTAG programming utility
    • Download the Digilent Plugin for Xlinx Tools.
    • Extract, and follow instructions in the enclosed Digilent_Plug-in_Xilinx_v14.pdf
    • Copy the files from the nt64 folder to C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64\plugins\Digilent\libCseDigilent\
  5. Later, to program using the JTAG interface
    • Xilinx ISE » Tools » iMPACT
    • Double-click boundary scan
    • Output -> Cable setup
      • select “Digilent USB JTAG cable”
      • the port will show your port(s)
      • speed = select speed
      • click Ok. The speed field will become empty. click Ok once more.
    • Right-click boundry window, and select Initialize chain (with the microboard connected)
      • set the configuration file (.bit)
      • select as target device
    • Save the prj.

A first circuit

I walked through the examples in the (old) book FPGA Prototyping with Verilog Examples. It targets Spartan 3, but still seems useful. In particular see chapter 2.6.1.

  1. Create a new design
    • Double-click the ISE icon on the desktop
    • File » New Project
      • location, working directory = ..
      • name = eq2
      • top level src type = HDL
      • Evaluation Dev Board = Avnet Spartan-6 LX9 MicroBoard
      • Synthesis tool = XST
      • Simulator = ISim
    • Project » New Source » Verilog Module
      • Enter port names
        • a input bus 1 0
        • b input bus 1 0
        • aeqb output
      • Use the text editor to enter the code eq2.v as shown below
        `timescale 1ns / 1ps
        module eq2(
             input [1:0] a,
             input [1:0] b,
             output aeqb
          wire e0, e1; // internal signal declaration
          eq1 eq_bit0_unit(.i0(a[0]), .i1(b[0]), .eq(e0));
          eq1 eq_bit1_unit(.i0(a[1]), .i1(b[1]), .eq(e1));
          assign aeqb = e0 & e1; // a and b are equal if individual bits are equal
    • Project » New Source » Verilog Module
      • Enter port names
        • i0 input
        • i1 input
        • eq output
      • Use the text editor to enter the code eq1.v as shown below
        `timescale 1ns / 1ps
        module eq1(
            input i0,
            input i1,
            output eq
          wire p0, p1; // internal signal declaration
          assign eq = p0 | p1 ;
          assign p0 = ~i0 & ~i1 ;
          assign p1 = i0 & i1 ;
    • Project » New Source » Implementation Constraints File
      • Enter the physical I/O pin assignments are user constraints.
      • Refer to the schematics, or hardware guide for details.
      • Use the text editor to enter the code eq2.ucf as shown below.
        CONFIG VCCAUX=3.3;
        NET a<0> LOC = B3 | IOSTANDARD = LVCMOS33 | PULLDOWN; #DIP switch-1
        NET a<1> LOC = A3 | IOSTANDARD = LVCMOS33 | PULLDOWN; #DIP switch-2
        NET b<0> LOC = B4 | IOSTANDARD = LVCMOS33 | PULLDOWN; #DIP switch-3
        NET b<1> LOC = A4 | IOSTANDARD = LVCMOS33 | PULLDOWN; #DIP switch-4
        NET aeqb LOC = P4 | IOSTANDARD = LVCMOS18;            #LED D2
    • Verify
      • Select the desired source file
      • In the process window (below), click the ‘+’ before “Synthesize – XST”
      • Double-click “Check Syntax”
      • The results will be shown in the transcript at the bottom
  2. Synthesis
    • Generates a .bit file to be uploaded to the FPGA later
    • Select the top-level verilog file (has a little green square in the icon)
      • In the Process Window, double click “Generate Programming File”
      • The transcript at the bottom will show the results
      • Correct problems if needed
      • Check the design summary (Process Windows » Design Summary)
  3. Create a test bench
    • Project » New Source » Verilog Test Fixture
    • name = eq2_test
    • associate with eq2
    • add the stimulus as shown in eq2_test.v below
      `timescale 1ns / 1ps
      module eq2_test;
        reg [1:0] a;  // inputs
        reg [1:0] b;
        wire aeqb;  // output
        // Instantiate the Unit Under Test (UUT)
        eq2 uut ( .a(a), 
                  .aeqb(aeqb) );
        initial begin
          a = 0;  // initialize inputs
          b = 0;
          #100;  // wait 100 ns for global reset to finish
          // stimulus starts here
          a = 2'b00; b = 2'b00; #100 $display("%b", aeqb);
          a = 2'b01; b = 2'b00; #100 $display("%b", aeqb);
          a = 2'b01; b = 2'b11; #100 $display("%b", aeqb);
          a = 2'b10; b = 2'b10; #100 $display("%b", aeqb);
          a = 2'b10; b = 2'b00; #100 $display("%b", aeqb);
          a = 2'b11; b = 2'b11; #100 $display("%b", aeqb);
          a = 2'b11; b = 2'b01; #100 $display("%b", aeqb);


  4. Behavior Simulation
    • Xilinx ISE comes packages with the ISim simulator. It is straightforward to use and fine for basic test benches. Other choices are ModelSim (hard to install under Windows 10, in my case the install suddenly continued after >24 hours), Active-HDL, and the online tool
    • Design Window (top left) » Simulation radio-button. In the drop-down list below it, select “Behavioral” view.
      • Select the eq2_test.v file
      • In the Process Window, double-click the Simulate Behavior Model
        • Will give a Windows Security Alert for isimgui.exe. Allow it access.
      • Navigate the ISim window to verify functionality. Use the F7 to zoom out. We expect an output like:
  5. Timing Simulation
    • In the Design Window (top left), select “Simulation”. In the drop down list below it, select “Post-Route”.
    • Select the eq2_test.v file
    • In the Process Window, double-click “Simulate Post-Place & Route Model”. This will reveal the timing delays as shown below
  6. Configure FPGA
    • Plug-in the USB type B connector from the LX9 microboard
    • Process Window » double click “Configure Target Device”
      • Before starting iMPACT, it will warn you that “No iMPACT project file exists”. Click OK to proceed.
      • Double-click “Boundary Scan”
      • Right-click in the right window, and select “Cable Setup”
        • Communication Mode = “Digilent USB JTAG cable”
        • Verify that port will show up
        • speed = select speed
        • click OK twice
      • Right-click in the right window, and select “Initialize chain”
        • assign the configuration file (.bit) created earlier
        • do not attached SPI or BPI PROM
        • click OK
        • right-click the Xilinx block, and select as “Set Target Device”
      • File » Save Project as “eq2” in the same directory as the source files.
        • Will tell you to “Set the new project file from the Configure Target Device process properties”. Don’t worry, it seems to do this automatically. Click OK to proceed.
      • Right-click the Xlilinx block, and select program.
        • This should report “Program Succeeded”
      • Close iMPACT, and save it once more on the way out.
  7. Give it a spin
    • It is finally time to try the real FPGA board
      • Input is through the DIP switches (SW1) on the left of the FPGA.
      • Output is the red LED (D2) located just below the FPGA.
      • We expect the LED to be “on” when switch position 1 and 2 are identical to position 3 and 4.
    • If you prefer bigger switches, I suggest wiring up a breadboard to PMOD1 (J5) connectors.
      • Vcc and Ground are available on respectively pin 5 (or 11) and 6 (or 12).
      • Remember to modify the user constraints file accordingly. For reference, I attached a fairly complete user constraints file spartan6-lx9.ucf.

See Xilinx’ student area for more info

c’est tout