# Instruction set

Introduces a simplified LC-3 instruction set, that we later will design a CPU for and implement in Verilog HDL.

## Instruction Set

The Instruction Set Architecture (ISA) specifies all the information to write a program in machine language. It contains:

• Memory organization, specifies the address maps; how many bits per location;
• Register set, specifies the size of the internal registers; how many registers; and how they can be used;
• Instruction set, specifies the opcodes; operands; data types; and addressing modes

### Simplicity rules

The book Introduction to Computer Systems by Patt and Partel, introduces an hypothetical microprocessor called LC-3. For this text we push the simplicity of this little computer (LC-3) even further by:

• not supporting subroutine calls, JSR JSRR RET
• not supporting interrupt handling, RTI TRAP
• not supporting overflow detection in arithmetic operations
• not validating the Instruction encoding
• replacing the TRAP 0, with a simple HALT instruction.

Implementing this very basic Instruction Set helps us understand the inner workings of a microprocessor.

With the exception of these simplifications, the Instruction Set Architecture (ISA) is specified in the book “Introduction to Computer Systems“. The following sections summarize this ISA. For more details, refer to Appendix A.3 of the book.

### Overview

• Memory organization:
• 16-bit memory words.
• Memory map
• User programs start at memory location 3000 hex, and may extend to FDFF.
• Bit numbering
• Bits are numbered from right (least significant bit) to left (most significant bit), starting with bit 0.
• Registers
• A 16-bit program counter (PC), contains the address of the next instruction.
• Eight 16-bit general purpose registers, numbered 000 .. 111 binary, for register R0 .. R7.
• A 3-bit processor status register (PSR), that is updated when an instructions writes to a register.
• psr[2]==1, when the 2’s complement value is negative (n).
• psr[1]==1, when the 2’s complement value is zero (z).
• psr[0]==1, when the 2’s complement value is positive (p).
• Instructions
• 16-bit instructions, RISC (all instructions the same size).
• the opcode, is encoded in the the 4 most significant bits of the instruction (bit 15..12).
• the operands, are encoded in the remaining 12 bits of the instruction.
• ALU performs ADD AND and NOT operations on 16-bit words.

### Instructions

#### Operand conventions

As mentioned above, from the 16 bit instruction, only 12 bits are available for the operands. This implies that 16-bit data values or memory addresses have to be specified indirectly. For instance by referring to a value in a register.

• PC relative, the address is calculated by adding an offset to the incremented program counter, pc.

The table below shows the conventions used in describing the instructions.

Operand Description
srID, sr1ID, sr2ID Source Register Identifiers (000..111 for R0..R7)
drID Destination Register Identifier (000..111 for R0..R7)
baseRID Base Register Identifier (000..111 for R0..R7)
sr, sr1, sr2 16-bit Source Register value
dr 16-bit Destination Register value
baseR Base Register value, used together with 2’s complement offset to calculate memory address.
imm5 5-bit immediate value as 2’s complement integer
offset6 6-bit value as 2’s complement integer
offset9 9-bit value as 2’s complement integer
SX Sign-extend, by replicating the most significant bit as many times as necessary to extend to the word size of 16 bits.
Conventions

#### ALU instructions

There are two variations of the ADD and AND instructions. The difference is in bit 5 of the instruction word. One takes the second argument from sr2, the other takes it from the immediate value imm5.

##### Instruction types

Opcode Name Assembly Operation
ADD DR, SR1, imm5 dr = sr1 + SX(imm5)
AND Logical AND AND DR, SR1, SR2 dr = sr1 & sr2
AND DR, SR1, imm5 dr = sr1 & SX(imm5)
NOT Logical NOT NOT DR, SR dr = ~sr

##### Instruction encoding

Opcode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD 0 0 0 1 drID sr1ID 0 0 0 sr2ID
0 0 0 1 drID sr1ID 1 imm5
AND 0 1 0 1 drID sr1ID 0 0 0 sr2ID
0 1 0 1 drID sr1ID 1 imm5
NOT 1 0 0 1 drID srID 1 1 1 1 1 1

#### Memory instructions

##### Instruction types

Opcode Name Assembly Operation
LD Load LD DR, label dr = mem[pc + SX(offset9)]
LDR Load Register LDR DR, BaseR, offset6 dr = mem[baseR + SX(offset6)]
LDI Load Indirect LDI DR, label dr = mem[mem[pc + SX(offset9)]]
LEA Load Eff. Addr. LEA DR, target dr = pc + SX(offset9)
ST Store ST SR, label mem[pc + SX(offset9)] = sr
STR Store Register STR SR, BaseR, offset6 mem[baseR + SX(offset6)] = sr
STI Store Indirect STI SR, label mem[mem[pc + SX(offset9)]] = sr

##### Instruction encoding

opcode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LD 0 0 1 0 drID offset9
LDR 0 1 1 0 drID baseRID offset6
LDI 1 0 1 0 drID offset9
LEA 1 1 1 0 drID offset9
ST 0 0 1 1 srID offset9
STR 0 1 1 1 srID baseRID offset6
STI 1 0 1 1 srID offset9

#### Control instructions

##### Instruction types

Opcode Name Assembly Operation
BR* Branch BR* label if (condition*) pc = pc + SX(offset9)
JMP Jump JMP BaseR pc = baseR
HALT Halt HALT stop program execution (simplified TRAP 0)

*) The assembler instruction for BR* can be either

• BRn label, test for state bit n
• BRz label, test for state bit z
• BRn label, test for state bit p
• BRzp label, test for state bits z and p
• BRnp label, test for state bits n and p
• BRnz label, test for state bits n and z
• BRnzp label, test for state bits n, z and p

##### Instruction encoding

opcode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR* 0 0 0 0 n z p offset9
JMP 1 1 0 0 0 0 0 baseRID 0 0 0 0 0 0
HALT 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 1

This article “Simplified LC-3 Instruction set” continues with Design on the next page.