Math Talk

This is the third part of the inquiry Math Talk. The prior pages described the SPI protocol and an implementation to move raw bytes between master and slave.

Message Exchange Protocol

The time has come to implement a status and register interface on top of the raw byte exchange. We define a few commands to retrieve the device status and access its 32-bit registers.


The first byte is defined as the command byte. The interpretation of the remaining bytes (if any) depends on this command. After the command is completed, a new command can be sent. The following commands will be supported:

  • Read status (0x00): Reads the status byte.
    • First the master sends 0x00, and ignores the value returned;
    • the master then sends one dummy byte, to get the 8-bit status value in return.
  • Read register (0x80 to 0x8F): Reads the value stored in one of the sixteen registers. The least significant four bits of the command indicate the register to read from.
    • First the master sends this command, and ignores the value returned;
    • then the master sends 4 dummy bytes to get the 32-bit register value. The first byte received is the most significant, the fourth is the least significant (network byte order).
  • Write register (0xC0 to 0xCF): Writes a value to one of the sixteen registers. The least significant four bits indicate the register to write to.
    • First the master sends the command, and ignores the value returned;
    • then the master sends 4 bytes with the value to write. The most significant byte is sent first, the least significant last.


The FPGA will implement two register types. The first 4 registers (0-3) are read/write and can be used to send information to the FPGA. The next 12 registers (4-15) are read-only to receive information from the FPGA. In the greater scheme, the read/write registers will be used to send math operands to the FPGA, and the read-only registers will be used to read the results from the FPGA.

Room for improvement

The protocol leaves some room for improvement. It can be made more efficient by implementing continuous commands. Here the master issues an read or write register start command, but keeps sending sets of 4-bytes until it has enough. Along similar lines one could implement commands to access attached memory.

The following pages describe an implementation that passes messages between an Arduino Master and FPGA Slave.

Embedded software developer
Passionately curious and stubbornly persistent. Enjoys to inspire and consult with others to exchange the poetry of logical ideas.

5 Replies to “Math Talk”

  1. Very well explained. I am looking some details with respect to interfacing Arduino with FPGA (Altera) using I2C where FPGA is a master and arduino is slave.

  2. Can we use this project to establish a communication between Arduino and FPGA?

  3. The Two-stage shift register here is used to synchronize only the serial clock coming from Master. Right? Or do we need to sync the rest signals (i.e MOSI, SS, MISO) ??

Leave a Reply

Your email address will not be published. Required fields are marked *


This site uses Akismet to reduce spam. Learn how your comment data is processed.