This is the second part of the inquiry Math Talk. In this part we describe the protocol used to transfer bytes between the microcontroller and FPGA.
Bytes Exchange Protocol
With the two devices physically connected, we need a protocol to transfer data. We chose the Serial Peripheral Interface (SPI), a lightweight protocol to connect one master to one or more slaves.
The SPI bus is controlled by a master device (typically a microcontroller) that orchestrates the bus access. The master generates the control signals and regulates the data flow. The illustration below shows a master with three slaves. The pinout for SCLK, MOSI, MISO and SS can be found on the previous page. The master uses the Slave Select (SS) signal to select the slave.
SPI is also a protocol with many degrees of freedom. It is important that the master and slave agree on the voltage levels and maximum clock frequency. The SPI clock polarity (CPOL) and clock phase (CPHA) introduce four more degrees of freedom as shown in the table below.
|Mode||CPOL||CPHA||clock idle||data driven||data latched|
|0||0||0||low||falling edge||rising edge|
|1||0||1||low||rising edge||falling edge|
|2||1||0||high||rising edge||falling edge|
|3||1||1||high||falling edge||rising edge|
For this article we assume mode 3, where the clock is high when idle; data is driving following the falling edge of the clock and latched on the rising edge.
The protocol is easiest explained with shift registers as shown in the illustration below. The master generates the SPI Clock (SCLK) to initiate the information exchange. Data is shifted on one edge of this clock and is sampled on the opposite edge when the data is stable.
In mode 3, at the falling edge of SCLK, both devices drive their most significant bit (b7) on their outgoing data line. On the rising edge, both devices clock in this bit into the least significant bit position (b0). After eight SCLK cycles, the master and slave have exchanged their values and each device processes the data received (e.g. writing it to memory). In case there is more data to be exchanged, the registers are loaded with new data and the process repeats itself. Once all data is transmitted, the master stops the SCLK clock.
For a more complete picture, we need to include the effect of the slave select (SS*) signal that is used to address the slave devices.
Slaves may only drive their output (MISO) line when SS* is active, otherwise they should tri-stated the output. The protocol can be broken down into the following steps:
- The master initiates the communication by activating SS*.
- The slave responds by starting to drive its MISO output.
- Meanwhile the master drives its MOSI output.
- The master makes SCLK low.
- On this falling edge, the master and slave drive their most significant bit position (b7) on respectively their MOSI and MISO outputs.
- The master makes SCLK high.
- On this rising edge, the master and slave clock the input from their respectively MISO and MOSI inputs into the least significant bit position (b0).
- Go back to step 2. until the least significant bit position (b0) has been sent.
- When all bits are transmitted, the master deactivates SS*.