This is the first part of the inquiry Math Talk We will describe the hardware components and the physical interconnect to communicate with the FPGA.
SPI is a protocol, in which one device (the master) controls one or more other devices (the slaves). For the master we use an open-source microcontroller prototyping platform, such as the Arduino 101 or a modified Arduino UNO R3. In this document we use Arduino to refer to either platform.
The slave can be a low-cost FPGA prototyping platforms, such as the Xilinx Spartan-6 Avnet LX9 or the Altera Cyclone-IV Terasic DE0-Nano. The repository includes project files and pin assignments for both these boards. The code is written in HDL Verilog and should work equally well on more powerful boards.
It is very important that the I/O voltage levels of the devices match. Both FPGA boards support 3.3V levels, and are a good match for the Arduino 101. However, the Arduino UNO uses the traditional 5 Volt TTL levels. Instead of using a level shifter, such as the 74LVC245, we opt for converting the Arduino to 3.3V according to Adafruit’s instructions. Running a 16 MHz clock at 3.3V is out of spec. Is said to work, but should really program the fuses to get the frequency down to abt. 13 MHz.
The SPI interface is a 4 wire interface. The bus consists of 3 signals plus a slave select signal for each device.
- SCLK, clock signal sent from the master to all slaves;
- MOSI, serial data from the master to the slaves (Master Out-Slave In);
- MISO, serial data from a slave to the master (Master In-Slave Out);
- SSn, slave select signal for each slave.
Once the Arduino runs at 3.3V, connecting the two devices becomes trivial.
The physical connections
|signal||Arduino||Xlinx FPGA||Altera FPGA|
|SS||Digital I/O 10||PMOD J4 pin1||GPIO0 J1 pin4|
|MOSI||Digital I/O 11||PMOD J4 pin2||GPIO0 J1 pin6|
|MISO||Digital I/O 12||PMOD J4 pin3||GPIO0 J1 pin8|
|SCK||Digital I/O 13||PMOD J4 pin4||GPIO0 J1 pin10|
|GND||GND||PMOD J4 pin5||GPIO0 J1 pin12|
The next page describes how to exchange bytes over this physical interface.