How do computers do math?

This is already the 6th part in a quest to answer the question “How do computers do math?” Here we introduce an improved transistor type and show how it can be used to build logic gates. \(\)[\latex]

Field Effect Transistor (FET)

The Field Effect Transistor (FET) model is “voltage to current amplifier” and can be used to build an amplifiers or as a voltage-controlled resistor.

Lilienfeld and Heil discovered the principle of Field-effect as early as 1926-1927, but it took until well after the invention of the bipolar junction transistor before they became practical (Atalla, 1960). Even though FETs are conceptually simple, they are difficult to manufacture because it requires an extremely clean manufacturing environment.

The illustration below shows the symbols for the JFETs and along with some samples.

Semiconductor Physics

In the n-channel device, the channel is in between two connected p-type regions, as shown in the illustration below. More heavily doped n+ type regions connect the source and drain pins to the n-type channel. This n+ type silicon prevents an unwanted pn-junction between the regular n-type silicon with four valence electrons and the e.g. aluminum terminal with three valence electrons.

When we place a modest voltage \(U_{ds}\) over the drain and source., the ions at the depletion layers give the channel a positive charge compared to the gate. The depletion layer is thicker towards the drain end of the channel, because the voltage on the drain is more positive than that on the source due to voltage gradient that exists along the channel. Current flows and the silicon channel acts rather like a conductor.

(c) 2016 Copyright Coert Vonk
N-channel JFET with Ugs=0

To use this JFET as a switch, we can increase the thickness of the depletion zone by applying a reverse bias on the gate, as shown below. This pushes the holes from the p-type region and the electrons in the n-type region away from the junction, increasing the width of the depletion zone. Eventually once enough potential is applied the transistor will pinch-off the channel current (\(I_d\)). This pinch-off voltage is typically a few volts negative.

To use this JFET as an amplifier, we would increase \(U_{ds}\) while \(U_{gs}=0\). At first you will see the drain current \(I_d\) increasing, but meanwhile the depletion layer also grow and narrow the n-channel. At the so called pinch-off value \(U_{p}\), the conducting channel is so narrow that it cancels out the effect of the higher \(U_{ds}\), and the \(I_d\) doesn’t increase much further, and the JFET is said to be in saturation mode. At this point, a small \(U_{gs}\) can be used to control the current through the source−drain channel from its maximum value to zero. [learn-electronics]

(c) 2016 Copyright Coert Vonk
N-channel JFET with Ugs

While these JFETs have very good properties, but once used in circuits, they still require bulky resistors. As we see in the next section, MOSFETs do not require such resistors.

Metal Oxide Silicon Field-effect Transistor (MOSFET)

At first glance, the construction of the MOSFET might appear similar to the JET. There are however some important differences: (1) a thin layer of silicon dioxide (SiO2) isolates the gate, and (2) there is no obvious conductive channel.

The illustration below shows symbols for the MOSFETs and various examples.

Semiconductor Physics

In the n-channel MOSFET, a p-type substrate connects to the source and drain pins via more heavily doped n+ type regions, as shown below. A very thin layer of silicon dioxide insulates the metal gate terminal from the substrate. A bias over the drain-source terminals causes the depletion layer around the drain to widen. The depletion areas prevent a drain current.

(c) 2016 Copyright Coert Vonk
N-channel MOSFET with Ugs=0

Applying a gate potential \(U_{gs}\) makes the gate positive with respect to the source and substrate, as shown below. The positive charge on the gate repels holes from the p-layer underneath, forming a depletion area. This charge also attracts free electrons from the n+ source and drain, that form a thin layer under the gate terminal bridging the source and drain areas. This layer is called an inversion channel because in effect it behaves like a n-type material. The inversion channel is of the same type, as the source and drain, and thus it provides a channel through which current can pass.

(c) 2016 Copyright Coert Vonk
N-channel MOSFET with Ugs

Any further increase of the gate voltage attracts more electrons into the inversion channel, reduces its resistance, and increases the current between source and drain. Removing the gate source voltage stops the current, and the area beneath the gate reverts to p-type. This method of operation is enhanced mode because the gate potential makes “enhances” the conducting channel. There are also devices where a gate potential “depletes” the conducting channel.

These MOSFET transistors draw very little power because the gate current is extremely low; their size is as small as 7 nanometers, the width of 10 silicon atoms; and can switch on/off in the order of GHz. This makes them an idea building block modern day computers that use integrated circuits with trillions of MOSFETS on one piece of silicon.

Field Effect Transistor based logic

A voltage input to the gate controls the flow of current from source to drain. Being voltage-controlled rather than current-controlled, it allows for circuits without resistors. CMOS draws no current, other than leakage, when in a steady 1 or 0 state. When the gate switches states, it draws current to charge the capacitance at the gate.

To implement logic functions, a complementary pair of MOSFETs can connect an output to either Vcc or Ground. The name Complementary Metal Oxide Semiconductor (CMOS) refers to the use of complementary pairs of p-type and n-type MOSFETs.

Use CMOS levels instead of TTL.

NOT gate in CMOS

The circuit shown below gives the most basic implementation of a CMOS gate, where the FETs are used invert a logical input signal.

When a 3.3 volt signal (logic 1) is applied at input \(A\), the n-channel MOSFET is conducting, and the p-channel MOSFET is not, and the output \(X\) is a logic 0. On the other hand, if the input is grounded (logic 0), the situation is reversed, and the output \(X\) is a logic 1. A simulation confirms that the output values stay well within the CMOS range.

\(U_A\) \(U_X\)
0 V 3.30 V
3.3 V 0.00 V

By extending this NOT gate, we can build NOR and NAND gates.

NOR gate in CMOS

Putting two n-channel MOSFET in parallel and two p-channel MOSFETS in series, creates a two-input NOR gate as shown in the circuit below. A simulation confirms that the output values stay perfectly within CMOS range.

(c) 2016 Copyright Coert Vonk
NOR gate in CMOS

\(U_A\) \(U_B\) \(U_X\)
0 V 0 V 3.30 V
0 V 3.3 V 0.00 V
3.3 V 0 V 0.00 V
3.3 V 3.3 V 0.00 V

NAND gate in CMOS

By putting two n-channel MOSFETs in series and two p-channel MOSFETS in parallel, we build a two-input NAND gate as shown in the circuit below. The simulation confirms that the output values stay at perfect CMOS values.

(c) 2016 Copyright Coert Vonk
NAND gate in CMOS

\(U_A\) \(U_B\) \(U_X\)
0 V 0 V 3.30 V
0 V 3.3 V 3.30 V
3.3 V 0 V 3.30 V
3.3 V 3.3 V 0.00 V

Now that we the gates worked out, the next chapter move on to combining these gates to build circuits that performs math operations. In doing so, we move close and close to answering our inquiry “How do computer do math”. More details can be found in the MIT handout CMOS Transistors, Gates, and Wires.

Embedded software developer
Passionately curious and stubbornly persistent. Enjoys to inspire and consult with others to exchange the poetry of logical ideas.

2 Replies to “How do computers do math?”

  1. Coert, I have tried to make a square root in excel but it would be work. The multiply and divide work in excel and the CSM works. I can not send you a picture of my work in this system. Can you help me?
    Ronald lokker from the Netherlands

  2. Thanks. I think the sqrt schematic might use the q* instead of the q to build the new subtrahend.
    [in parallel to email conversation]

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